The present invention relates to an improved process for fabricating semiconductor devices that contain a low-resistivity metal interconnect and a low-dielectric-constant dielectric layer. More specifically, the present invention relates to an improved process which protects the low-dielectric-constant (i.e., low-K) dielectric layer from being degraded by, for example, a plasma etching process, during the fabricating semiconductor devices that contain a copper or other low-resistivity metal interconnect embedded a low-dielectric-constant dielectric layer. The method of the present invention simplifies the copper based semiconductor device fabrication process by allowing the copper interconnect to be formed subsequent to the formation of the low-K dielectric layer without an extra dielectric pattern process. The method disclosed in the present invention is most advantageous in fabricating semiconductors involving the use of the conventional dual damascene process.
The trend in the semiconductor industry is to use copper metal as interconnect material in the so-called damascene or dual damascene processes. Damascene is an interconnection fabrication process in which grooves are formed in an insulating layer which are then filled with metal to form the conductive lines that interconnect the component parts of the integrated circuit. Dual damascene is a multi-level interconnection process in which via openings, typically in the form of tungsten plugs, are formed in addition to forming the grooves of the single damascene process. Conductive lines, or the so-called xe2x80x9cinterconnectsxe2x80x9d, are then deposited that interconnect the active and passive elements of the integrated circuit contained on the semiconductor chip.
Copper metal has been increasingly used as a replacement material for aluminum and aluminum-silicon alloys in VLSI and ULSI metallization to form the interconnections because it has better conductivity and is more reliable than other metals including the commonly used aluminum and aluminum alloys. However, one of the technical problems in using the copper metal is that copper atoms will still diffuse into silicon or other adjacent material(s) if applied directly to the silicon without first applying a barrier layer between the silicon layer and the copper layer. In conventional aluminum interconnect structures, the barrier layer is usually not required between the aluminum metal line and an SiO2 inter-level dielectric (ILD). When copper is utilized, however, the copper metal must be encapsulated from the surrounding ILD, since copper atoms can easily diffuse into the adjoining dielectric. Once the copper reaches the silicon substrate, it will significantly degrade the device""s performance.
Because copper encapsulation is a necessary step requiring a presence of a barrier material to separate the copper layer, other materials, such as a low-dielectric constant (low-K) material, can now be advantageously used as substitutes for the SiO2 as the ILD material. A low-K material is defined as an dielectric material having a dielectric constant less than that of SiO2, which has a dielectric constant of about 4. There are generally two types of low-K materials for semiconductor fabrication processes: (1) modified SiO2 materials, such as fluorinated oxide (add limited F into SiO2) and silsesquioxane (add limited H or C-based organic elements to SiO2); and (2) organic materials, such as polyimides and polymers, having completely different molecular structures in comparison to SiO2. Replacing the conventional SiO2 material by a low-K material reduces the interline capacitance, thereby reducing the RC delay, cross-talk noise and power dissipation in the interconnect. One advantage of organic low-K materials is that they offer a lower dielectric constant than the modified SiO2 materials.
Quite a few prior art references have extensively discussed the fabrication of semiconductor devices that contain copper interconnects and low-K dielectric layer. For example, U.S. Pat. No. 5,965,934 discloses a semiconductor device formed on a wafer comprising source and drain regions contacted by source and drain contacts, respectively. Each source and drain region is separated by a gate region contacted by a gate electrode, with a first level patterned interconnect contacting the source and drain contacts and the gate electrode in a predetermined pattern and with a second level patterned interconnect contacting the first level patterned interconnect by a plurality of metal lines.
The metal lines are separated by a first dielectric material, and the second level patterned interconnect comprises a low resistance metal wherein the low resistance metal is selected from the group consisting of copper, gold, silver, and platinum and separated by a planarized dielectric material inert to diffusion of the low resistance metal. The planarized dielectric material, which provides a diffusion barrier to the low resistance metal, is benzocyclobutene or a derivative thereof.
U.S. Pat. No. 6,096,648 discloses a metallization process which includes the steps of first forming a dielectric layer on the surface of a silicon layer. Next, a barrier layer is deposited on the surface of the dielectric layer, after which, a copper seed layer is deposited on the barrier layer. After the copper seed layer is deposited, the semiconductor chip is annealed to restore any crystal damage that might have occurred when the copper seed layer and the barrier layer were deposited, and to control copper film properties. After the formation of cooper lines, a low dielectric constant layer is then deposited on the surface of the semiconductor chip. The low dielectric constant layer fills the gaps between the copper lines with a non-conductive material. In one embodiment, a barrier layer is formed separating the low dielectric constant layer from the cooper layer.
U.S. Pat. No. 6,100,184 discloses a technique for fabricating a dual damascene interconnect structure on a semiconductor chip using a low dielectric constant (low-K) organic material as a dielectric layer or layers. The process disclosed in the ""184 patent comprises the steps of: (a) depositing a barrier layer and a copper seed layer on the semiconductor chip; (b) annealing the semiconductor chip after the copper seed layer is deposited; (c) using microlithography to form a patterned photoresist layer on the copper seed layer; (d) electroplating a copper conductive layer on the semiconductor chip; (e) stripping off the patterned photoresist layer and portions of the barrier layer and the copper seed layer that were located beneath the patterned photoresist layer; and (f) depositing a low dielectric constant layer on the semiconductor chip.
In all the processes described above, the low-K dielectric layer was always formed after the formation of the copper interconnect. It is desirable to form the copper interconnect by first forming the low-K dielectric layer, patterning the low-K dielectric layer, and then filling in the trenches formed in the low-K dielectric layer. However, the need to form a barrier layer between the copper interconnect and the low-K dielectric layer necessitates a plasma etching process after the low-K dielectric layer is formed. It was discovered by the inventors of the present invention that the plasma etching process can materially and adversely affect the integrity of the low-K dielectric layer. This problem has resulted in lowered production yield.
The primary object of the present invention is to develop an improved for the fabrication of cooper-based semiconductors. More specifically, the primary object of the present invention is to develop a method that will improve the process for fabricating semiconductor devices which utilize copper or other low-resistivity metal as interconnects and which include a low-K (low dielectric constant) dielectric layer. A low-K dielectric layer is important in a copper-based semiconductor device to minimize the diffusion of the low resistance metal. The present invention allows the copper interconnect to be formed subsequent to the formation of the low-K dielectric layer, while preventing the low-K dielectric from being subject to a plasma etching process, which can cause the integrity of the low-K dielectric layer to be degraded. The method disclosed in the present invention is most advantageous in fabricating semiconductors using the conventional dual damascene process, where to conductive layers are separated by an inter-level dielectric (ILD) but connected by conductive vias.
The process disclosed in the present invention, which is to form a copper interconnect on a semiconductor wafer according to a predetermined pattern, can be summarized as comprising the following main steps:
(1) Forming a silica glass layer on a wafer surface;
(2) Photolithographically patterning the silica glass layer according to the predetermined copper interconnect pattern;
(3) Conformably depositing a dielectric layer on the silica glass layer;
(4) Anisotropically etching the dielectric layer to form a sidewall spacer;
(5) Depositing a low-K (low dielectric constant) dielectric layer on the wafer, covering the silica glass and the sidewall spacer;
(6) Planarizing the low-dielectric layer;
(7) Photolithographically removing the silica glass layer to form a trench in the low- dielectric layer; and
(8) Depositing a conductive material to fill the trench.
One of the key elements of the present invention is to form a pseudo-metal line from the silica glass layer mimicking copper interconnect that is to be eventually patterned. This allows the metal interconnect to be formed subsequent to the formation of the low-K dielectric layer. It also allows the dielectric side barrier (in the form of sidewall spacer) to be formed by plasma etching before the formation of the low-K dielectric layer. The former improves the precision of the metal interconnect pattern without the extra step of forming an additional dielectric layer, and the latter helps retaining the integrity of the low-K dielectric layer by eliminating a subsequent plasma etch stage, which would have been necessary if the dielectric sidewall barrier were formed after the low-K dielectric layer.
The process of the present invention is most advantageous for forming semiconductor devices wherein the conductive material is a low-resistivity metal such as copper, gold, silver, etc., or most advantageously copper. After the trench is filled with the conductive material, it is planarized by a chemical-mechanical polishing (CMP) process. Prior to the metal filling step, a thin barrier metal layer can be deposited in the trench. A silicon nitride layer can be deposited on the metal layer and the low-K dielectric layer for protection against future processes.